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Personal Details
NameDr PALLAB NATH
DesignationAssistant Professor
DepartmentElectronics and Communication Engineering, School of Technology
EmailPallab.Nath@sot.pdpu.ac.in
Educational Qualifications
  • Ph.D (VLSI and Microelectronics, IIT Kharagpur), 2018
  • M.Tech. (VLSI and Microelectronics, Bengal Engineering and Science University, Shibpur (Presently IIEST Shibpur)), 2009
  • B.Tech. (Electronics and Communication Engineering, West Bengal University of Technology, Kolkata), 2005
    Professional Affiliation
    Fraunhofer Institute for Integrated Circuits (IIS)- Germany, IISc. Bangalore, IIT Kharagpur, NIT Raipur, IIITDM Kurnool
    Awards
    1. Received ERCIM - Alain Bensoussan fellowship for pursuing Post-Doc at Fraunhofer IIS - Germany (2024). 2. Received CSIR Senior Research Associateship (CSIR-SRA) for pursuing Post-Doc at IISc. Bangalore (2021). 2. Received (as a team) Gandhian Young Technological Innovation (GYTI 2018) Appreciation Award in MLM (More form Less for Many) category for the project “Smartphone based portable low-cost continuous wave Doppler Ultrasound system”
    Publications / Articles / Conference
    Published Papers in Journals
  • 'A single-chip solution for diagnosing peripheral arterial disease', IEEE Transactions on Very Large Scale Integration, May 2022
  • 'Multiplierless MP-Kernel Machine For Energy-efficient Edge Devices', IEEE Transactions on Very Large Scale Integration, Aug 2022
  • 'Efficient partial product reduction for image processing application using approximate 4:2 compression', Circuit World, Sep 2021
  • 'A high throughput pass parallel block decoder architecture for JPEG 2000 that prevents stalling in the decoding process', Integration, the VLSI Journal, Elsevier, Mar 2020
  • 'High Throughput Unified Architecture of LEA Algorithm for Image Encryption', Microprocessors and Microsystems, Elsevier, Oct 2020
  • 'Smartphone based point-of-care system using continuous wave portable Doppler', IEEE Transactions on Instrumentation and Measurement, Oct 2020
  • 'A high speed, memory efficient line based VLSI architecture for the dual mode inverse discrete wavelet transform of JPEG2000 decoder', Microprocessors and Microsystems, Elsevier, Feb 2016
    Papers presented in Conferences, Seminars, Workshops, Symposia

  • 'Multiplierless In-filter Computing for tinyML Platforms', 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems (VLSID), jan 2024
  • 'FPGA based Compressive Sensing Framework for Video Compression on Edge Devices', 24th International Symposium on VLSI Design and Test (VDAT), Jun 2020
  • 'An Efficient Hardware Implementation of Walsh Hadamard Transform for JPEG XR ', 15th Edition of the IEEE India Council International Conference (INDICON 2018), Dec 2018